A phase lock loop (PLL) is an important apparatus for numerous applications. A PLL receives a reference clock and generates accordingly an output clock that is phase locked with the reference clock. A phase lock loop typically comprises a controller and a controlled oscillator. The controlled oscillator outputs an output clock with a frequency controlled by a control signal generated by the controller. The output clock is usually divided down by a factor of N, where N is an integer, resulting in a divided-down clock. The controller issues the control signal based on detecting a phase difference between a reference clock and the divided down clock. The frequency of the output clock is thus controlled in a closed-loop manner so as to minimize the phase difference between the reference clock and the divided-down clock. In a steady state, the output clock is thus phase locked with the reference clock.
In a typical PLL, the controller comprises a phase detector and a filter. The phase detector receives the reference clock and the divided-down clock and outputs a detector output signal representing the phase difference between the reference clock and the divided-down clock. The filter receives and converts the detector output signal into the control signal to control the controlled oscillator. In a typical PLL, the phase detector comprises a PFD (phase/frequency detector) and a charge pump circuit, and the resultant detector output signal is a current-mode signal. The filter filters and converts the current-mode detector output signal into a voltage-mode control signal to control the oscillator, which is a voltage-controlled oscillator (VCO). Modern phase lock loops are usually implemented in a CMOS (complementary metal-oxide semiconductor) integrated circuit. In a deep submicron CMOS integrated circuit, high-speed devices of short channel lengths are prone to charge leakage. In particular, the charge pump circuit, whose purpose is to generate the detector output signal to represent the phase difference between the reference clock and the divided-down clock, is prone to charge leakage. This effectively introduces an error in the phase detection, which results in an error in the voltage-mode control signal and thus an error in the phase/frequency of the output clock. The error in the phase/frequency of the output clock is generally referred to as clock jitter.
What is needed is a method to reduce the clock jitter due to charge leakage of the charge pump circuit.